Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 342 of 547
NXP Semiconductors
UM10398
Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer
18.7.11 Count Control Register (TMR16B0CTCR and TMR16B1CTCR)
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edges for counting.
When Counter Mode is chosen as a mode of operation, the CAP input (selected by the
CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two
consecutive samples of this CAP input, one of the following four events is recognized:
rising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event occurs, and the event corresponds to the one selected by
bits 1:0 in the CTCR register, will the Timer Counter register be incremented.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one half of the
PCLK clock. Consequently, duration of the HIGH/LOW levels on the same CAP input in
this case can not be shorter than 1/(2  PCLK).
9:8 EMC2 External Match Control 2. Determines the functionality of External Match 2. 00
0x0 Do Nothing.
0x1 Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if
pinned out).
0x2 Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if
pinned out).
0x3 Toggle the corresponding External Match bit/output.
11:10 EMC3 External Match Control 3. Determines the functionality of External Match 3. 00
0x0 Do Nothing.
0x1 Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if
pinned out).
0x2 Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if
pinned out).
0x3 Toggle the corresponding External Match bit/output.
31:12 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 291. External Match Register (TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address
0x4001 003C) bit description
Bit Symbol Value Description Reset
value
Table 292. External match control
EMR[11:10], EMR[9:8],
EMR[7:6], or EMR[5:4]
Function
00 Do Nothing.
01 Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if
pinned out).
10 Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if
pinned out).
11 Toggle the corresponding External Match bit/output.