Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 343 of 547
NXP Semiconductors
UM10398
Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer
18.7.12 PWM Control register (TMR16B0PWMC and TMR16B1PWMC)
The PWM Control Register is used to configure the match outputs as PWM outputs. Each
match output can be independently set to perform either as PWM output or as match
output whose function is controlled by the External Match Register (EMR).
For timer 0, three single-edge controlled PWM outputs can be selected on the
CT16B0_MAT[2:0] outputs. For timer 1, two single-edged PWM outputs can be selected
on the CT16B1_Mat[1:0] outputs. One additional match register determines the PWM
cycle length. When a match occurs in any of the other match registers, the PWM output is
set to HIGH. The timer is reset by the match register that is configured to set the PWM
cycle length. When the timer is reset to zero, all currently HIGH match outputs configured
as PWM outputs are cleared.
Table 293. Count Control Register (TMR16B0CTCR - address 0x4000 C070 and
TMR16B1CTCR - address 0x4001 0070) bit description
Bit Symbol Value Description Reset
value
1:0 CTM Counter/Timer Mode. This field selects which rising PCLK
edges can increment Timer’s Prescale Counter (PC), or clear
PC and increment Timer Counter (TC).
00
0x0 Timer Mode: every rising PCLK edge
0x1 Counter Mode: TC is incremented on rising edges on the
CAP input selected by bits 3:2.
0x2 Counter Mode: TC is incremented on falling edges on the
CAP input selected by bits 3:2.
0x3 Counter Mode: TC is incremented on both edges on the CAP
input selected by bits 3:2.
3:2 CIS Count Input Select. In counter mode (when bits 1:0 in this
register are not 00), these bits select which CAP pin is
sampled for clocking. Note: If Counter mode is selected in
the CTCR register, bits 2:0 in the Capture Control Register
(CCR) must be programmed as 000.
00
0x0 CT16Bn_CAP0
0x1 CT16Bn_CAP1
0x2 Reserved.
0x3 Reserved.
31:4 - - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
-
Table 294. PWM Control Register (TMR16B0PWMC - address 0x4000 C074 and
TMR16B1PWMC- address 0x4001 0074) bit description
Bit Symbol Value Description Reset
value
0 PWMEN0 PWM channel0 enable 0
0 CT16Bn_MAT0 is controlled by EM0.
1 PWM mode is enabled for CT16Bn_MAT0.