Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 345 of 547
NXP Semiconductors
UM10398
Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer
18.8 Example timer operation
Figure 70 shows a timer configured to reset the count and generate an interrupt on match.
The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle
where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 71
shows a timer configured to stop and generate an interrupt on match. The
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
Fig 69. Sample PWM waveforms with a PWM cycle length of 100 (selected by MR2) and
MAT2:0 enabled as PWM outputs by the PWCM register.
100
(counter is reset)
04165
PWM0/MAT0
PWM1/MAT1
PWM2/MAT2 MR2 = 100
MR1 = 41
MR0 = 65
Fig 70. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled
PCLK
prescale
counter
interrupt
timer
counter
timer counter
reset
222200001111
45 6 0 1
Fig 71. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled
PCLK
prescale counter
interrupt
timer counter
TCR[0]
(counter enable)
220 01
45 6
1 0