Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 346 of 547
NXP Semiconductors
UM10398
Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer
18.9 Architecture
The block diagram for counter/timer0 and counter/timer1 is shown in Figure 72.
Fig 72. 16-bit counter/timer block diagram
reset
MAXVAL
TIMER CONTROL REGISTER PRESCALE REGISTER
PRESCALE COUNTER
PCLK
enable
CAPTURE REGISTER 0
MATCH REGISTER 3
MATCH REGISTER 2
MATCH REGISTER 1
MATCH REGISTER 0
CAPTURE CONTROL REGISTER
CONTROL
TIMER COUNTER
CSN
TCI
CE
=
=
=
=
INTERRUPT REGISTER
EXTERNAL MATCH REGISTER
MATCH CONTROL REGISTER
MATn[2:0]
INTERRUPT
CAP0
STOP ON MATCH
RESET ON MATCH
LOAD[3:0]