Datasheet

User manual Rev. 12.3 — 10 June 2014 347 of 547

19.1 How to read this chapter

The 16-bit timer blocks are identical for all LPC1100XL parts.

Compared to the timer block for the LPC1100/LPC1100L/LPC1100C series, the following

features have been added:

• One additional capture input for each timer.

• Capture-clear function for easy pulse-width measurement (see Section 19.7.11).

19.2 Basic configuration

The CT16B0/1 are configured using the following registers:

1. Pins: The CT16B0/1 pins must be configured in the IOCONFIG register block

(Section 7.4

2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 7 and bit 8

(Table 21

). The peripheral clock is provided by the system clock (see Table 20).

19.3 Features

• Two 16-bit counter/timers with a programmable 16-bit prescaler.

• Counter or timer operation.

• The timer and prescaler may be configured to be cleared on a designated capture

event. This feature permits easy pulse-width measurement by clearing the timer on

the leading edge of an input pulse and capturing the timer value on the trailing edge.

• Two 16-bit capture channels that can take a snapshot of the timer value when an input

signal transitions. A capture event may also optionally generate an interrupt.

• Four 16-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to three (CT16B0) or two (CT16B1) external outputs corresponding to match

registers with the following capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

• For each timer, up to four match registers can be configured as PWM allowing to use

up to three match outputs as single edge controlled PWM outputs.

UM10398

Chapter 19: LPC1100XL series: 16-bit counter/timer CT16B0/1

Rev. 12.3 — 10 June 2014 User manual