Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 357 of 547
NXP Semiconductors
UM10398
Chapter 19: LPC1100XL series: 16-bit counter/timer CT16B0/1
19.7.11 Count Control Register (TMR16B0CTCR and TMR16B1CTCR)
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting.
When Counter Mode is chosen as a mode of operation, the CAP input (selected by the
CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two
consecutive samples of this CAP input, one of the following four events is recognized:
rising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event occurs, and the event corresponds to the one selected by
bits 1:0 in the CTCR register, will the Timer Counter register be incremented.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one half of the
PCLK clock. Consequently, duration of the HIGH/LOW levels on the same CAP input in
this case can not be shorter than 1/(2  PCLK).
Bits 7:4 of this register are used to enable and configure the capture-clears-timer feature.
This feature allows for a designated edge on a particular CAP input to reset the timer to all
zeros. Using this mechanism to clear the timer on the leading edge of an input pulse and
performing a capture on the trailing edge permits direct pulse-width measurement using a
single capture input without the need to perform a subtraction operation in software.
Table 309. Count Control Register (TMR16B0CTCR - address 0x4000 C070 and
TMR16B1CTCR - address 0x4001 0070) bit description
Bit Symbol Value Description Reset
value
1:0 CTM Counter/Timer Mode. This field selects which rising PCLK
edges can increment Timer’s Prescale Counter (PC), or clear
PC and increment Timer Counter (TC).
00
0x0 Timer Mode: every rising PCLK edge
0x1 Counter Mode: TC is incremented on rising edges on the
CAP input selected by bits 3:2.
0x2 Counter Mode: TC is incremented on falling edges on the
CAP input selected by bits 3:2.
0x3 Counter Mode: TC is incremented on both edges on the CAP
input selected by bits 3:2.
3:2 CIS Count Input Select. In counter mode (when bits 1:0 in this
register are not 00), these bits select which CAP pin is
sampled for clocking. Note: If Counter mode is selected in
the CTCR register, bits 2:0 in the Capture Control Register
(CCR) must be programmed as 000.
00
0x0 CT16Bn_CAP0
0x1 CT16Bn_CAP1
0x2 Reserved.
0x0 Reserved.
4 ENCC Setting this bit to one enables clearing of the timer and the
prescaler when the capture-edge event specified in bits 7:5
occurs.
0