Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 362 of 547
20.1 How to read this chapter
The 32-bit timer blocks are identical for all LPC111x, LPC11D14, and LPC11Cxx parts.
20.2 Basic configuration
The CT32B0/1 are configured using the following registers:
1. Pins: The CT32B0/1 pins must be configured in the IOCONFIG register block
(Section 7.4
).
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 9 and bit 10
(Table 21
). The peripheral clock (PCLK) is provided by the system clock (see
Table 20
).
20.3 Features
• Two 32-bit counter/timers with a programmable 32-bit prescaler.
• Counter or Timer operation.
• One 32-bit capture channel that can take a snapshot of the timer value when an input
signal transitions. A capture event may also optionally generate an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Four external outputs corresponding to match registers with the following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• For each timer, up to four match registers can be configured as PWM allowing to use
up to three match outputs as single edge controlled PWM outputs.
20.4 Applications
• Interval timer for counting internal events
• Pulse Width Demodulator via capture input
• Free running timer
• Pulse Width Modulator via match outputs
UM10398
Chapter 20: LPC1100/LPC1100C/LPC1100L series: 32-bit
counter/timer CT32B0/1
Rev. 12.3 — 10 June 2014 User manual