Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 37 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
3.5.23 CLKOUT clock divider register
This register determines the divider value for the clock output signal on the CLKOUT pin.
3.5.24 POR captured PIO status register 0
The PIOPORCAP0 register captures the state (HIGH or LOW) of the PIO pins of ports 0,1,
and 2 (pins PIO2_0 to PIO2_7) at power-on-reset. Each bit represents the reset state of
one GPIO pin. This register is a read-only status register.
3.5.25 POR captured PIO status register 1
The PIOPORCAP1 register captures the state (HIGH or LOW) of the PIO pins of port 2
(PIO2_8 to PIO2_11) and port 3 at power-on-reset. Each bit represents the reset state of
one PIO pin. This register is a read-only status register.
Table 30. CLKOUT clock divider registers (CLKOUTCLKDIV, address 0x4004 80E8) bit
description
Bit Symbol Description Reset value
7:0 DIV Clock output divider values
0: Disable CLKOUT.
1: Divide by 1.
to
255: Divide by 255.
0x00
31:8 - Reserved 0x00
Table 31. POR captured PIO status registers 0 (PIOPORCAP0, address 0x4004 8100) bit
description
Bit Symbol Description Reset value
11:0 CAPPIO0_n Raw reset status input PIO0_n:
PIO0_11 to PIO0_0
User implementation dependent
23:12 CAPPIO1_n Raw reset status input PIO1_n:
PIO1_11 to PIO1_0
User implementation dependent
31:24 CAPPIO2_n Raw reset status input PIO2_n:
PIO2_7 to PIO2_0
User implementation dependent
Table 32. POR captured PIO status registers 1 (PIOPORCAP1, address 0x4004 8104) bit
description
Bit Symbol Description Reset value
0 CAPPIO2_8 Raw reset status input PIO2_8 User implementation dependent
1 CAPPIO2_9 Raw reset status input PIO2_9 User implementation dependent
2 CAPPIO2_10 Raw reset status input PIO2_10 User implementation dependent
3 CAPPIO2_11 Raw reset status input PIO2_11 User implementation dependent
4 CAPPIO3_0 Raw reset status input PIO3_0 User implementation dependent
5 CAPPIO3_1 Raw reset status input PIO3_1 User implementation dependent
6 CAPPIO3_2 Raw reset status input PIO3_2 User implementation dependent
7 CAPPIO3_3 Raw reset status input PIO3_3 User implementation dependent
8 CAPPIO3_4 Raw reset status input PIO3_4 User implementation dependent
9 CAPPIO3_5 Raw reset status input PIO3_5 User implementation dependent
31:10 - Reserved -