Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller HVQFN 32 (7x7) 32-Bit 50 MHz I/O number 28

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User manual Rev. 12.3 — 10 June 2014 373 of 547

NXP Semiconductors

UM10398

Chapter 20: LPC1100/LPC1100C/LPC1100L series: 32-bit counter/timer

20.7.13 Rules for single edge controlled PWM outputs

1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle

(timer is set to zero) unless their match value is equal to zero.

2. Each PWM output will go HIGH when its match value is reached. If no match occurs

(i.e. the match value is greater than the PWM cycle length), the PWM output remains

continuously LOW.

3. If a match value larger than the PWM cycle length is written to the match register, and

the PWM signal is HIGH already, then the PWM signal will be cleared with the start of

the next PWM cycle.

4. If a match register contains the same value as the timer reset value (the PWM cycle

length), then the PWM output will be reset to LOW on the next clock tick after the

timer reaches the match value. Therefore, the PWM output will always consist of a

one clock tick wide positive pulse with a period determined by the PWM cycle length

(i.e. the timer reload value).

5. If a match register is set to zero, then the PWM output will go to HIGH the first time the

timer goes back to zero and will stay HIGH continuously.

Note: When the match outputs are selected to function as PWM outputs, the timer reset

(MRnR) and timer stop (MRnS) bits in the Match Control Register MCR must be set to 0

except for the match register setting the PWM cycle length. For this register, set the

MRnR bit to 1 to enable the timer reset when the timer value matches the value of the

corresponding match register.

1 PWMEN1 PWM channel 1 enable 0

0 CT32Bn_MAT1 is controlled by EM1.

1 PWM mode is enabled for CT32Bn_MAT1.

2 PWMEN2 PWM channel 2 enable 0

0 CT32Bn_MAT2 is controlled by EM2.

1 PWM mode is enabled for CT32Bn_MAT2.

3 PWMEN3 PWM channel 3 enable

Note: It is recommended to use match channel 3 to set

the PWM cycle.

0 CT32Bn_MAT3 is controlled by EM3.

1 PWM mode is enabled for CT32Bn_MAT3.

31:4 - Reserved, user software should not write ones to

reserved bits. The value read from a reserved bit is not

defined.

Table 326: PWM Control Register (TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC -

0x4001 8074) bit description

Bit Symbol Value Description Reset

value