Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 38 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
3.5.26 BOD control register
The BOD control register selects up to four separate threshold values for sending a BOD
interrupt to the NVIC and for forced reset. Reset and interrupt threshold values listed are
typical values.
3.5.27 System tick counter calibration register
This register determines the value of the SYST_CALIB register (see Table 361).
3.5.28 IRQ latency register
The IRQLATENCY register is an eight-bit register which specifies the minimum number of
cycles (0-255) permitted for the system to respond to an interrupt request. The intent of
this register is to allow the user to select a trade-off between interrupt response time and
determinism.
Table 33. BOD control register (BODCTRL, address 0x4004 8150) bit description
Bit Symbol Value Description Reset
value
1:0 BODRSTLEV BOD reset level 00
0x0 Level 0: The reset assertion threshold voltage is 1.46 V; the
reset de-assertion threshold voltage is 1.63 V.
0x1 Level 1: The reset assertion threshold voltage is 2.06 V; the
reset de-assertion threshold voltage is 2.15 V.
0x2 Level 2: The reset assertion threshold voltage is 2.35 V; the
reset de-assertion threshold voltage is 2.43 V.
0x3 Level 3: The reset assertion threshold voltage is 2.63 V; the
reset de-assertion threshold voltage is 2.71 V.
3:2 BODINTVAL BOD interrupt level 00
0x0 Level 0: Reserved.
0x1 Level 1:The interrupt assertion threshold voltage is 2.22 V;
the interrupt de-assertion threshold voltage is 2.35 V.
0x2 Level 2: The interrupt assertion threshold voltage is 2.52 V;
the interrupt de-assertion threshold voltage is 2.66 V.
0x3 Level 3: The interrupt assertion threshold voltage is 2.80 V;
the interrupt de-assertion threshold voltage is 2.90 V.
4 BODRSTENA BOD reset enable 0
0 Disable reset function.
1 Enable reset function.
31:5 - - Reserved 0x00
Table 34. System tick timer calibration register (SYSTCKCAL, address 0x4004 8154) bit
description
Bit Symbol Description Reset
value
25:0 CAL System tick timer calibration value 0x04
31:26 - Reserved 0x00