Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 381 of 547
NXP Semiconductors
UM10398
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
21.7.4 Prescale Register (TMR32B0PR - address 0x4001 400C and
TMR32B1PR - address 0x4001 800C)
The 32-bit Prescale Register specifies the maximum value for the Prescale Counter.
21.7.5 Prescale Counter Register (TMR32B0PC - address 0x4001 4010 and
TMR32B1PC - address 0x4001 8010)
The 32-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship between the resolution
of the timer and the maximum time before the timer overflows. The Prescale Counter is
incremented on every PCLK. When it reaches the value stored in the Prescale Register,
the Timer Counter is incremented, and the Prescale Counter is reset on the next PCLK.
This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when
PR = 1, etc.
21.7.6 Match Control Register (TMR32B0MCR and TMR32B1MCR)
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in Table 335
.
Table 333: Prescale registers (TMR32B0PR, address 0x4001 400C and TMR32B1PR
0x4001 800C) bit description
Bit Symbol Description Reset
value
31:0 PR Prescale value. 0
Table 334: Prescale counter registers (TMR32B0PC, address 0x4001 4010 and TMR32B1PC
0x4001 8010) bit description
Bit Symbol Description Reset
value
31:0 PC Prescale counter value. 0
Table 335: Match Control Register (TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014)
bit description
Bit Symbol Value Description Reset
value
0 MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0
1 Enabled
0 Disabled
1 MR0R Reset on MR0: the TC will be reset if MR0 matches it. 0
1 Enabled
0 Disabled
2 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches
the TC.
0
1 Enabled
0 Disabled