Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 383 of 547
NXP Semiconductors
UM10398
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
21.7.8 Capture Control Register (TMR32B0CCR and TMR32B1CCR)
The Capture Control Register is used to control whether the Capture Register is loaded
with the value in the Timer Counter when the capture event occurs, and whether an
interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, “n” represents the Timer number, 0 or 1.
Table 336: Match registers (TMR32B0MR0 to 3, addresses 0x4001 4018 to 24 and
TMR32B1MR0 to 3, addresses 0x4001 8018 to 24) bit description
Bit Symbol Description Reset
value
31:0 MATCH Timer counter match value. 0
Table 337: Capture Control Register (TMR32B0CCR - address 0x4001 4028 and TMR32B1CCR - address
0x4001 8028) bit description
Bit Symbol Value Description Reset
value
0 CAP0RE Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will
cause CR0 to be loaded with the contents of TC.
0
1 Enabled
0 Disabled
1 CAP0FE Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will
cause CR0 to be loaded with the contents of TC.
0
1 Enabled
0 Disabled
2 CAP0I Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will
generate an interrupt.
0
1 Enabled
0 Disabled
3 CAP1RE Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will
cause CR1 to be loaded with the contents of TC.
0
1 Enabled
0 Disabled
4 CAP1FE Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will
cause CR1 to be loaded with the contents of TC.
0
1 Enabled
0 Disabled
5 CAP1I Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will
generate an interrupt.
0
1 Enabled
0 Disabled
31:6 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA