Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 384 of 547
NXP Semiconductors
UM10398
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
21.7.9 Capture Register (TMR32B0CR0/1 - address 0x4001 402C/30 and
TMR32B1CR0/1 - address 0x4001 802C/30)
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
21.7.10 External Match Register (TMR32B0EMR and TMR32B1EMR)
The External Match Register provides both control and status of the external match pins
CAP32Bn_MAT[3:0].
If the match outputs are configured as PWM output, the function of the external match
registers is determined by the PWM rules (Section 21.8.2 “
Rules for single edge
controlled PWM outputs” on page 389).
Table 338: Capture registers (TMR32B0CR0/1, addresses 0x4001 402C/30 and
TMR32B1CR0/1, addresses 0x4001 802C/30) bit description
Bit Symbol Description Reset
value
31:0 CAP Timer counter capture value. 0
Table 339: External Match Register (TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C)
bit description
Bit Symbol Value Description Reset
value
0 EM0 External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this
output is connected to its pin. When a match occurs between the TC and MR0, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality
of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0
1 EM1 External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this
output is connected to its pin. When a match occurs between the TC and MR1, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality
of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0
2 EM2 External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this
output is connected to its pin. When a match occurs between the TC and MR2, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality
of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0
3 EM3 External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this
output is connected to its pin. When a match occurs between the TC and MR3, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the
functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if
the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0