Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 388 of 547
NXP Semiconductors
UM10398
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
21.8 Functional description
21.8.1 Example timer operation
Figure 81 shows a timer configured to reset the count and generate an interrupt on match.
The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle
where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 82
shows a timer configured to stop and generate an interrupt on match. The
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
3 PWMEN3 PWM channel 3 enable
Note: It is recommended to use match channel 3 to set
the PWM cycle.
0
0 CT32Bn_MAT3 is controlled by EM3.
1 PWM mode is enabled for CT32Bn_MAT3.
31:4 - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
Table 342: PWM Control Register (TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC -
0x4001 8074) bit description
Bit Symbol Value Description Reset
value
Fig 81. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled
PCLK
prescale
counter
interrupt
timer
counter
timer counter
reset
222200001111
45 6 0 1