Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 39 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
Setting this parameter to a very low value (e.g. zero) will guarantee the best possible
interrupt performance but will also introduce a significant degree of uncertainty and jitter.
Requiring the system to always take a larger number of cycles (whether it needs it or not)
will reduce the amount of uncertainty but may not necessarily eliminate it.
Theoretically, the ARM Cortex-M0 core should always be able to service an interrupt
request within 15 cycles. System factors external to the cpu, however, bus latencies,
peripheral response times, etc. can increase the time required to complete a previous
instruction before an interrupt can be serviced. Therefore, accurately specifying a
minimum number of cycles that will ensure determinism will depend on the application.
The default setting for this register is 0x010.
3.5.29 NMI source selection register
The NMI source selection register selects a peripheral interrupts as source for the NMI
interrupt of the ARM Cortex-M0 core. For a list of all peripheral interrupts and their IRQ
numbers see Table 55
. For a description of the NMI functionality, see Section 28.4.3.2.
Remark: See Section 3.1
for LPC111x parts using this register.
Note: If the NMISRC register is used to select an interrupt as the source of Non-Maskable
interrupts, and the selected interrupt is enabled, one interrupt request can result in both a
Non-Maskable and a normal interrupt. Avoid this situation by disabling the normal
interrupt in the NVIC, as described in Section 28.6.2
.
3.5.30 Start logic edge control register 0
The STARTAPRP0 register controls the start logic inputs of ports 0 (PIO0_0 to PIO0_11)
and 1 (PIO1_0). This register selects a falling or rising edge on the corresponding PIO
input to produce a falling or rising clock edge, respectively, for the start logic (see
Section 3.10.2
).
Every bit in the STARTAPRP0 register controls one port input and is connected to one
wake-up interrupt in the NVIC. Bit 0 in the STARTAPRP0 register corresponds to interrupt
0, bit 1 to interrupt 1, etc. (see Table 55
), up to a total of 13 interrupts.
Table 35. IRQ latency register (IRQLATENCY, address 0x4004 8170) bit description
Bit Symbol Description Reset
value
7:0 LATENCY 8-bit latency value 0x010
31:8 - Reserved -
Table 36. NMI source selection register (NMISRC, address 0x4004 8174) bit description
Bit Symbol Description Reset
value
4:0 IRQNO The IRQ number of the interrupt that acts as the Non-Maskable Interrupt
(NMI) if bit 31 in this register is 1. See Table 55
for the list of interrupt
sources and their IRQ numbers.
0
30:5 - Reserved -
31 NMIEN Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source
selected by bits 4:0.
0