Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 392 of 547
NXP Semiconductors
UM10398
Chapter 22: LPC111x/LPC11Cxx Windowed WatchDog Timer (WDT)
• Flag to indicate Watchdog reset.
22.4 Applications
The purpose of the Watchdog Timer is to reset the microcontroller within a reasonable
amount of time if it enters an erroneous state. When enabled, a watchdog event will be
generated if the user program fails to feed (or reload) the Watchdog within a
predetermined amount of time. The Watchdog event will cause a chip reset if configured
to do so.
When a watchdog window is programmed, an early watchdog feed is also treated as a
watchdog event. This allows preventing situations where a system failure may still feed
the watchdog. For example, application code could be stuck in an interrupt service that
contains a watchdog feed. Setting the window such that this would result in an early feed
will generate a watchdog event, allowing for system recovery.
.
22.5 General description
The Watchdog consists of a fixed divide-by-4 pre-scaler and a 24-bit counter which
decrements when clocked. The minimum value from which the counter decrements is
0xFF. Setting a value lower than 0xFF causes 0xFF to be loaded in the counter. Hence the
minimum Watchdog interval is (T
WDCLK
 256  4) and the maximum Watchdog interval is
(T
WDCLK
 2
24
 4) in multiples of (T
WDCLK
 4). The Watchdog should be used in the
following manner:
• Set the Watchdog timer constant reload value in WDTC register.
• Setup the Watchdog timer operating mode in WDMOD register.
• Set a value for the watchdog window time in WDWINDOW register if windowed
operation is required.
• Set a value for the watchdog warning interrupt in the WDWARNINT register if a
warning interrupt is required.
• Enable the Watchdog by writing 0xAA followed by 0x55 to the WDFEED register.
• The Watchdog must be fed again before the Watchdog counter reaches zero in order
to prevent a watchdog event. If a window value is programmed, the feed must also
occur after the watchdog counter passes that value.
When the Watchdog Timer is configured so that a watchdog event will cause a reset and
the counter reaches zero, the CPU will be reset, loading the stack pointer and program
counter from the vector table as in the case of external reset. The Watchdog time-out flag
(WDTOF) can be examined to determine if the Watchdog has caused the reset condition.
The WDTOF flag must be cleared by software.
When the Watchdog Timer is configured to generate a warning interrupt, the interrupt will
occur when the counter matches the value defined by the WDWARNINT register.
The block diagram of the Watchdog is shown below in the Figure 85
. The synchronization
logic (PCLK - WDCLK) is not shown in the block diagram.