Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 394 of 547
NXP Semiconductors
UM10398
Chapter 22: LPC111x/LPC11Cxx Windowed WatchDog Timer (WDT)
22.7 Register description
The Watchdog contains the registers shown in Table 343.
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
22.7.1 Watchdog Mode register
The WDMOD register controls the operation of the Watchdog as per the combination of
WDEN and RESET bits. Note that a watchdog feed must be performed before any
changes to the WDMOD register take effect.
Table 343. Register overview: Watchdog timer (base address 0x4000 4000)
Name Access Address
offset
Description Reset value
[1]
WDMOD R/W 0x000 Watchdog mode register. This register contains the basic mode and
status of the Watchdog Timer.
0
WDTC R/W 0x004 Watchdog timer constant register. This register determines the
time-out value.
0xFF
WDFEED WO 0x008 Watchdog feed sequence register. Writing 0xAA followed by 0x55 to
this register reloads the Watchdog timer with the value contained in
WDTC.
-
WDTV RO 0x00C Watchdog timer value register. This register reads out the current
value of the Watchdog timer.
0xFF
WDWARNINT R/W 0x014 Watchdog Warning Interrupt compare value. 0
WDWINDOW R/W 0x018 Watchdog Window compare value. 0xFF FFFF
Table 344: Watchdog Mode register (WDMOD - 0x4000 4000) bit description
Bit Symbol Value Description Reset
value
0 WDEN Watchdog enable bit. This bit is Set Only.
Remark: Setting this bit to one also locks the
watchdog clock source. Once the watchdog timer is
enabled, the watchdog timer clock source cannot be
changed. If the watchdog timer is needed in
Deep-sleep mode, the watchdog clock source must be
changed to the watchdog oscillator before setting this
bit to one.
0
0 The watchdog timer is stopped.
1 The watchdog timer is running.
1 WDRESET Watchdog reset enable bit. This bit is Set Only. 0
0 A watchdog timeout will not cause a chip reset.
1 A watchdog timeout will cause a chip reset.
2 WDTOF Watchdog time-out flag. Set when the watchdog timer
times out, by a feed error, or by events associated with
WDPROTECT, cleared by software. Causes a chip
reset if WDRESET = 1.
0 (Only
after
external
reset)
3 WDINT Watchdog interrupt flag. Set when the timer reaches
the value in WDWARNINT. Cleared by software.
0