Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 403 of 547
NXP Semiconductors
UM10398
Chapter 23: LPC111x/LPC11Cxx WatchDog Timer (WDT)
Interrupts should be disabled during the feed sequence. An abort condition will occur if an
interrupt happens during the feed sequence.
23.7.4 Watchdog Timer Value register (WDTV - 0x4000 400C)
The WDTV register is used to read the current value of Watchdog timer.
When reading the value of the 24-bit timer, the lock and synchronization procedure takes
up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual
value of the timer when it's being read by the CPU.
23.8 Block diagram
The block diagram of the Watchdog is shown below in the Figure 89. The synchronization
logic (PCLK/WDCLK) is not shown in the block diagram.
Table 355. Watchdog Feed register (WDFEED - address 0x4000 4008) bit description
Bit Symbol Description Reset Value
7:0 Feed Feed value should be 0xAA followed by 0x55. NA
31:8 - Reserved -
Table 356. Watchdog Timer Value register (WDTV - address 0x4000 000C) bit description
Bit Symbol Description Reset Value
23:0 Count Counter timer value. 0x0000 00FF
31:24 - Reserved -
Fig 89. Watchdog block diagram
WDTC
24-BIT DOWN COUNTER
WDINT WDTOF WDRESET WDEN
SHADOW BIT
reset
interrupt
4
WDFEED
feed ok
feed error
wdt_clk
underflow
enable
count
WMOD register
feed sequence