Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 404 of 547
24.1 How to read this chapter
The system tick timer (SysTick timer) is part of the ARM Cortex-M0 core and is identical
for all LPC111x, LPC11D14, and LPC11Cxx parts.
24.2 Basic configuration
The system tick timer is configured using the following registers:
1. Pins: The system tick timer uses no external pins.
2. Power: The system tick timer is enabled through the SysTick control register
SYST_CSR (Table 358
). The SysTick control register also allows changing the clock
source to the SysTick timer
3. Enable the clock source for the SysTick timer in the SYST_CSR register (Table 358
).
24.3 Features
• Simple 24-bit timer.
• Uses dedicated exception vector.
• Clocked internally by the system clock or the system clock/2.
24.4 General description
The block diagram of the SysTick timer is shown below in the Figure 90.
The SysTick timer is an integral part of the Cortex-M0. The SysTick timer is intended to
generate a fixed 10 millisecond interrupt for use by an operating system or other system
management software.
UM10398
Chapter 24: LPC111x/LPC11Cxx System tick timer (SysTick)
Rev. 12.3 — 10 June 2014 User manual
Fig 90. System tick timer block diagram
system clock
reference clock
= system clock/2
SYST_CALIB
SYST_RVR
SYST_CVR
24-bit down counter
ENABLE
SYST_CSR
private
peripheral
bus
System Tick
interrupt
TICKINTCOUNTFLAG
load
under-
flow
count
enable
clock
load data
1
0
SYST_CSR
bit CLKSOURCE