Datasheet

User manual Rev. 12.3 — 10 June 2014 405 of 547

NXP Semiconductors

UM10398

Chapter 24: LPC111x/LPC11Cxx System tick timer (SysTick)

Since the SysTick timer is a part of the Cortex-M0, it facilitates porting of software by

providing a standard timer that is available on Cortex-M0 based devices. The SysTick

timer can be used for:

• An RTOS tick timer which fires at a programmable rate (for example 100 Hz) and

invokes a SysTick routine.

• A high-speed alarm timer using the core clock.

• A simple counter. Software can use this to measure time to completion and time used.

• An internal clock source control based on missing/meeting durations. The

COUNTFLAG bit-field in the control and status register can be used to determine if an

action completed within a set duration, as part of a dynamic clock management

control loop.

Refer to the Cortex-M0 User Guide for details.

24.5 Register description

The systick timer registers are located on the ARM Cortex-M0 private peripheral bus (see

Figure 98

), and are part of the ARM Cortex-M0 core peripherals. For details, see

Section 28.6.4

[1] Reset Value reflects the data stored in used bits only. It does not include content of reserved bits.

24.5.1 System Timer Control and status register

The SYST_CSR register contains control information for the SysTick timer and provides a

status flag. This register is part of the ARM Cortex-M0 core system timer register block.

For a bit description of this register, see Section 28.6.4 “

System timer, SysTick”.

This register determines the clock source for the system tick timer.

Table 357. Register overview: SysTick timer (base address 0xE000 E000)

Name Access Address

offset

Description Reset value

[1]

SYST_CSR R/W 0x010 System Timer Control and status register 0x000 0000

SYST_RVR R/W 0x014 System Timer Reload value register 0

SYST_CVR R/W 0x018 System Timer Current value register 0

SYST_CALIB R/W 0x01C System Timer Calibration value register 0x4