Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 408 of 547
25.1 How to read this chapter
The ADC block is identical for all LPC111x, LPC11D14, and LPC11Cxx parts.
All HVQFN33 and LQFP48 packages support eight ADC channels. On the small
packages (TSSOP28/DIP28/TSSOP20/SO20), only five or six ADC channels are pinned
out (see Table 3
).
25.2 Basic configuration
The ADC is configured using the following registers:
1. Pins: The ADC pin functions are configured in the IOCONFIG register block
(Section 7.4
).
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 13 (Table 21
).
Power to the ADC at run-time is controlled through the PDRUNCFG register
(Table 44
).
Remark: Basic clocking for the A/D converters is determined by the APB clock (PCLK). A
programmable divider is included in the A/D converter to scale this clock to the 4.5 MHz
(max) clock needed by the successive approximation process. An accurate conversion
requires 11 clock cycles.
25.3 Features
• 10-bit successive approximation Analog-to-Digital Converter (ADC).
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range 0 to 3.6 V. Do not exceed the V
DD
voltage level.
• 10-bit conversion time  2.44 s.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or Timer Match signal.
• Individual result registers for each A/D channel to reduce interrupt overhead.
25.4 Pin description
Table 362 gives a brief summary of the ADC related pins.
UM10398
Chapter 25: LPC111x/LPC11Cxx ADC
Rev. 12.3 — 10 June 2014 User manual