Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 409 of 547
NXP Semiconductors
UM10398
Chapter 25: LPC111x/LPC11Cxx ADC
The ADC function must be selected via the IOCON registers in order to get accurate
voltage readings on the monitored pin. For a pin hosting an ADC input, it is not possible to
have a have a digital function selected and yet get valid ADC readings. An inside circuit
disconnects ADC hardware from the associated pin whenever a digital function is selected
on that pin.
25.5 Register description
The ADC contains registers organized as shown in Table 363.
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Table 362. ADC pin description
Pin Type Description
AD[7:0] Input Analog Inputs. The A/D converter cell can measure the voltage on any
of these input signals.
Remark: While the pins are 5 V tolerant in digital mode, the maximum
input voltage must not exceed V
DD
when the pins are configured as
analog inputs.
V
DD
Input V
REF
; Reference voltage.
Table 363. Register overview: ADC (base address 0x4001 C000)
Name Access Address
offset
Description Reset
Value
[1]
AD0CR R/W 0x000 A/D Control Register. The AD0CR register must be written to select the
operating mode before A/D conversion can occur.
0x0000 0000
AD0GDR R/W 0x004 A/D Global Data Register. Contains the result of the most recent A/D
conversion.
NA
- - 0x008 Reserved. -
AD0INTEN R/W 0x00C A/D Interrupt Enable Register. This register contains enable bits that allow
the DONE flag of each A/D channel to be included or excluded from
contributing to the generation of an A/D interrupt.
0x0000 0100
AD0DR0 R/W 0x010 A/D Channel 0 Data Register. This register contains the result of the most
recent conversion completed on channel 0
NA
AD0DR1 R/W 0x014 A/D Channel 1 Data Register. This register contains the result of the most
recent conversion completed on channel 1.
NA
AD0DR2 R/W 0x018 A/D Channel 2 Data Register. This register contains the result of the most
recent conversion completed on channel 2.
NA
AD0DR3 R/W 0x01C A/D Channel 3 Data Register. This register contains the result of the most
recent conversion completed on channel 3.
NA
AD0DR4 R/W 0x020 A/D Channel 4 Data Register. This register contains the result of the most
recent conversion completed on channel 4.
NA
AD0DR5 R/W 0x024 A/D Channel 5 Data Register. This register contains the result of the most
recent conversion completed on channel 5.
NA
AD0DR6 R/W 0x028 A/D Channel 6 Data Register. This register contains the result of the most
recent conversion completed on channel 6.
NA
AD0DR7 R/W 0x02C A/D Channel 7 Data Register. This register contains the result of the most
recent conversion completed on channel 7.
NA
AD0STAT RO 0x030 A/D Status Register. This register contains DONE and OVERRUN flags for
all of the A/D channels, as well as the A/D interrupt flag.
0