Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 41 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
3.5.33 Start logic status register 0
This register reflects the status of the enabled start signal bits. The bit assignment is
identical to Table 37
. Each bit (if enabled) reflects the state of the start logic, i.e. whether
or not a wake-up signal has been received for a given pin.
3.5.34 Deep-sleep mode configuration register
This register controls the behavior of the WatchDog (WD) oscillator and the BOD circuit
when the device enters Deep-sleep mode.
This register must be initialized at least once before entering Deep-sleep mode with
one of the four values shown in Table 41
:
Remark: Failure to initialize and program this register correctly may result in undefined
behavior of the microcontroller. The values listed in Table 41
are the only values allowed
for PDSLEEPCFG register.
To select the appropriate power configuration for Deep-sleep mode, consider the
following:
• BOD: Leaving the BOD circuit enabled will protect the part from a low voltage event
occurring while the part is in Deep-sleep mode. However, the BOD circuit causes an
additional current drain in Deep-sleep mode.
• WD oscillator: The watchdog oscillator can be left running in Deep-sleep mode to
provide a clock for the watchdog timer or a general purpose timer if they are needed
for timing a wake-up event (see Section 3.10.3
for details). In this case, the watchdog
oscillator analog output frequency must be set to its lowest value (bits FREQSEL in
the WDTOSCCTRL = 0001, see Table 13
) and all peripheral clocks other than the
timer clock must be disabled in the SYSAHBCLKCTRL register (see Table 21
) before
entering Deep-sleep mode.
The watchdog oscillator, if running, contributes an additional current drain in
Deep-sleep mode.
Remark: Reserved bits in this register must always be written as indicated. This register
must be initialized correctly before entering Deep-sleep mode.
Table 40. Start logic status register 0 (STARTSRP0, address 0x4004 820C) bit description
Bit Symbol Description Reset
value
11:0 SRPIO0_n Start signal status for start logic input PIO0_n: PIO0_11 to
PIO0_0
0 = No start signal received.
1 = Start signal pending.
n/a
12 SRPIO1_0 Start signal status for start logic input PIO1_0
0 = No start signal received.
1 = Start signal pending.
n/a
31:13 - Reserved n/a
Table 41. Allowed values for PDSLEEPCFG register
Configuration WD oscillator on WD oscillator off
BOD on PDSLEEPCFG = 0x0000 18B7 PDSLEEPCFG = 0x0000 18F7
BOD off PDSLEEPCFG = 0x0000 18BF PDSLEEPCFG = 0x0000 18FF