Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 412 of 547
NXP Semiconductors
UM10398
Chapter 25: LPC111x/LPC11Cxx ADC
25.5.3 A/D Interrupt Enable Register (AD0INTEN - 0x4001 C00C)
This register allows control over which A/D channels generate an interrupt when a
conversion is complete. For example, it may be desirable to use some A/D channels to
monitor sensors by continuously performing conversions on them. The most recent
results are read by the application program whenever they are needed. In this case, an
interrupt is not desirable at the end of each conversion for some A/D channels.
25.5.4 A/D Data Registers (AD0DR0 to AD0DR7 - 0x4001 C010 to
0x4001 C02C)
The A/D Data Register hold the result when an A/D conversion is complete, and also
include the flags that indicate when a conversion has been completed and when a
conversion overrun has occurred.
Table 366. A/D Interrupt Enable Register (AD0INTEN - address 0x4001 C00C) bit description
Bit Symbol Description Reset
Value
7:0 ADINTEN These bits allow control over which A/D channels generate
interrupts for conversion completion. When bit 0 is one, completion
of a conversion on A/D channel 0 will generate an interrupt, when bit
1 is one, completion of a conversion on A/D channel 1 will generate
an interrupt, etc.
0x00
8 ADGINTEN When 1, enables the global DONE flag in AD0DRx to generate an
interrupt. When 0, only the individual A/D channels enabled by
ADINTEN 7:0 will generate interrupts.
Remark: This bit must be set to 0 in burst mode (BURST = 1 in the
AD0CR register).
1
31:9 - Reserved. Unused, always 0. 0
Table 367. A/D Data Registers (AD0DR0 to AD0DR7 - addresses 0x4001 C010 to
0x4001 C02C) bit description
Bit Symbol Description Reset
Value
5:0 - Reserved. 0
15:6 V_VREF When DONE is 1, this field contains a binary fraction representing the
voltage on the ADn pin, divided by the voltage on the V
REF
pin. Zero in
the field indicates that the voltage on the ADn pin was less than, equal
to, or close to that on V
REF
, while 0x3FF indicates that the voltage on
AD input was close to, equal to, or greater than that on V
REF
.
NA
29:16 - Reserved. 0
30 OVERRUN This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced
the result in the V_VREF bits.This bit is cleared by reading this
register.
0
31 DONE This bit is set to 1 when an A/D conversion completes. It is cleared
when this register is read.
0