Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 42 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
3.5.35 Wake-up configuration register
The bits in this register determine the state the chip enters when it is waking up from
Deep-sleep mode.
By default, the IRC and flash memory are powered and running and the BOD circuit is
enabled when the chip wakes up from Deep-sleep mode.
Remark: Reserved bits must be always written as indicated.
Table 42. Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit
description
Bit Symbol Value Description Reset
value
2:0 NOTUSED Reserved. Always write these bits as 111. 0
3 BOD_PD BOD power-down control in Deep-sleep mode, see
Table 41
.
0
0 Powered
1 Powered down
5:4 NOTUSED Reserved. Always write these bits as 11. 0
6 WDTOSC_PD Watchdog oscillator power control in Deep-sleep
mode, see Table 41
.
0
0 Powered
1 Powered down
7 NOTUSED Reserved. Always write this bit as 1. 0
10:8 NOTUSED Reserved. Always write these bits as 000. 0
12:11 NOTUSED Reserved. Always write these bits as 11. 0
31:13 - 0 Reserved 0
Table 43. Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit
description
Bit Symbol Value Description Reset
value
0 IRCOUT_PD IRC oscillator output wake-up configuration 0
0 Powered
1 Powered down
1 IRC_PD IRC oscillator power-down wake-up configuration 0
0 Powered
1 Powered down
2 FLASH_PD Flash wake-up configuration 0
0 Powered
1 Powered down
3 BOD_PD BOD wake-up configuration 0
0 Powered
1 Powered down