Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 420 of 547
NXP Semiconductors
UM10398
Chapter 26: LPC111x/LPC11Cxx Flash programming firmware
26.3.7 Flash content protection mechanism
The LPC111x/LPC11C1x is equipped with the Error Correction Code (ECC) capable Flash
memory. The purpose of an error correction module is twofold. Firstly, it decodes data
words read from the memory into output data words. Secondly, it encodes data words to
be written to the memory. The error correction capability consists of single bit error
correction with Hamming code.
The operation of ECC is transparent to the running application. The ECC content itself is
stored in a flash memory not accessible by user’s code to either read from it or write into it
on its own. A byte of ECC corresponds to every consecutive 128 bits of the user
accessible Flash. Consequently, Flash bytes from 0x0000 0000 to 0x0000 000F are
protected by the first ECC byte, Flash bytes from 0x0000 0010 to 0x0000 001F are
protected by the second ECC byte, etc.
Whenever the CPU requests a read from user’s Flash, both 128 bits of raw data
containing the specified memory location and the matching ECC byte are evaluated. If the
ECC mechanism detects a single error in the fetched data, a correction will be applied
before data are provided to the CPU. When a write request into the user’s Flash is made,
write of user specified content is accompanied by a matching ECC value calculated and
stored in the ECC memory.
When a sector of Flash memory is erased, the corresponding ECC bytes are also erased.
Once an ECC byte is written, it can not be updated unless it is erased first. Therefore, for
the implemented ECC mechanism to perform properly, data must be written into the flash
memory in groups of 16 bytes (or multiples of 16), aligned as described above.
26.3.8 Code Read Protection (CRP)
Code Read Protection is a mechanism that allows the user to enable different levels of
security in the system so that access to the on-chip flash and use of the ISP can be
restricted. When needed, CRP is invoked by programming a specific pattern in flash
location at 0x0000 02FC. IAP commands are not affected by the code read protection.
Important: any CRP change becomes effective only after the device has gone
through a power cycle.
13 4 208 - 223 0x0000 D000 - 0x0000 DFFF - - - - - yes yes
144224 - 2390x0000 E000 - 0x0000 EFFF- - ----yes
15 4 240 - 255 0x0000 F000 - 0x0000 FFFF - - - ---yes
Table 371. LPC1100XL flash configuration
Sector
number
Sector
size
[kB]
Page
number
Address range
LPC1111 (8 kB flash) LPC1112 (16 kB flash) LPC1113 (24 kB flash) LPC1114/203/303 (32 kB flash) LPC1114/323 (48 kB flash) LPC1114/333 (56 kB flash) LPC1115 (64 kB flash)