Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 43 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
3.5.36 Power-down configuration register
The bits in the PDRUNCFG register control the power to the various analog blocks. This
register can be written to at any time while the chip is running, and a write will take effect
immediately with the exception of the power-down signal to the IRC.
To avoid glitches when powering down the IRC, the IRC clock is automatically switched off
at a clean point. Therefore, for the IRC a delay is possible before the power-down state
takes effect.
By default, the IRC and flash memory are powered and running and the BOD circuit is
enabled.
Remark: Reserved bits must be always written as indicated.
4 ADC_PD ADC wake-up configuration 1
0 Powered
1 Powered down
5 SYSOSC_PD System oscillator wake-up configuration 1
0 Powered
1 Powered down
6 WDTOSC_PD Watchdog oscillator wake-up configuration 1
0 Powered
1 Powered down
7 SYSPLL_PD System PLL wake-up configuration 1
0 Powered
1 Powered down
8 - Reserved. Always write this bit as 1. 1
9 - Reserved. Always write this bit as 0. 0
10 - Reserved. Always write this bit as 1. 1
11 - Reserved. Always write this bit as 1. 1
12 - Reserved. Always write this bit as 0. 0
15:13 - Reserved. Always write these bits as 111. 111
31:16 - - Reserved -
Table 43. Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit
description
…continued
Bit Symbol Value Description Reset
value
Table 44. Power-down configuration register (PDRUNCFG, address 0x4004 8238) bit
description
Bit Symbol Value Description Reset
value
0 IRCOUT_PD IRC oscillator output power-down 0
0 Powered
1 Powered down