Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 456 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
[1] Describes access type during program execution in thread mode and Handler mode. Debug access can
differ.
[2] Bit[24] is the T-bit and is loaded from bit[0] of the reset vector.
28.4.1.3.1 General-purpose registers
R0-R12 are 32-bit general-purpose registers for data operations.
28.4.1.3.2 Stack Pointer
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register
indicates the stack pointer to use:
• 0 = Main Stack Pointer (MSP). This is the reset value.
• 1 = Process Stack Pointer (PSP).
Fig 96. Processor core register set
Table 420. Core register set summary
Name Type
[1]
Reset value Description
R0-R12 RW Unknown Section 28–28.4.1.3.1
MSP RW See description Section 28–28.4.1.3.2
PSP RW Unknown Section 28–28.4.1.3.2
LR RW Unknown Section 28–28.4.1.3.3
PC RW See description Section 28–28.4.1.3.4
PSR RW Unknown
[2]
Table 28–421
APSR RW Unknown Table 28–422
IPSR RO 0x00000000 Table 423
EPSR RO Unknown
[2]
Table 28–424
PRIMASK RW 0x00000000 Table 28–425
CONTROL RW 0x00000000 Table 28–426
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