Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 459 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
Attempts by application software to read the EPSR directly using the
MRS
instruction
always return zero. Attempts to write the EPSR using the
MSR
instruction are ignored.
Fault handlers can examine the EPSR value in the stacked PSR to determine the cause
of the fault. See Section 28–28.4.3.6
. The following can clear the T bit to 0:
• instructions
BLX
,
BX
and
POP{PC}
• restoration from the stacked xPSR value on an exception return
• bit[0] of the vector value on an exception entry.
Attempting to execute instructions when the T bit is 0 results in a HardFault or lockup. See
Section 28–28.4.4.1
for more information.
Interruptible-restartable instructions: The interruptible-restartable instructions are
LDM
and
STM
. When an interrupt occurs during the execution of one of these instructions, the
processor abandons execution of the instruction.
After servicing the interrupt, the processor restarts execution of the instruction from the
beginning.
28.4.1.3.6 Exception mask register
The exception mask register disables the handling of exceptions by the processor.
Disable exceptions where they might impact on timing critical tasks or code sequences
requiring atomicity.
To disable or re-enable exceptions, use the
MSR
and
MRS
instructions, or the
CPS
instruction, to change the value of PRIMASK. See Section 28–28.5.7.6
,
Section 28–28.5.7.7
, and Section 28–28.5.7.2 for more information.
Priority Mask Register: The PRIMASK register prevents activation of all exceptions with
configurable priority. See the register summary in Table 28–420
for its attributes. The bit
assignments are:
28.4.1.3.7 CONTROL register
The CONTROL register controls the stack used when the processor is in Thread mode.
See the register summary in Table 28–420
for its attributes. The bit assignments are:
Table 424. EPSR bit assignments
Bits Name Function
[31:25] - Reserved
[24] T Thumb state bit
[23:0] - Reserved
Table 425. PRIMASK register bit assignments
Bits Name Function
[31:1] - Reserved
[0] PRIMASK 0 = no effect
1 = prevents the activation of all exceptions with
configurable priority.