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ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller HVQFN 32 (7x7) 32-Bit 50 MHz I/O number 28

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User manual Rev. 12.3 — 10 June 2014 460 of 547

NXP Semiconductors

UM10398

Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference

Handler mode always uses the MSP, so the processor ignores explicit writes to the active

stack pointer bit of the CONTROL register when in Handler mode. The exception entry

and return mechanisms update the CONTROL register.

In an OS environment, it is recommended that threads running in Thread mode use the

process stack and the kernel and exception handlers use the main stack.

By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode

to the PSP, use the

MSR

instruction to set the Active stack pointer bit to 1, see

Section 28–28.5.7.6

Remark: When changing the stack pointer, software must use an

ISB

instruction

immediately after the

MSR

instruction. This ensures that instructions after the ISB execute

using the new stack pointer. See Section 28–28.5.7.5

28.4.1.4 Exceptions and interrupts

The Cortex-M0 processor supports interrupts and system exceptions. The processor and

the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An

interrupt or exception changes the normal flow of software control. The processor uses

handler mode to handle all exceptions except for reset. See Section 28–28.4.3.6.1

and

Section 28–28.4.3.6.2

for more information.

The NVIC registers control interrupt handling. See Section 28–28.6.2

for more

information.

28.4.1.5 Data types

The processor:

• supports the following data types:

– 32-bit words

– 16-bit halfwords

– 8-bit bytes

• manages all data memory accesses as little-endian. Instruction memory and Private

Peripheral Bus (PPB) accesses are always little-endian. See Section 28–28.4.2.1

for

more information.

28.4.1.6 The Cortex Microcontroller Software Interface Standard

ARM provides the Cortex Microcontroller Software Interface Standard (CMSIS) for

programming Cortex-M0 microcontrollers. The CMSIS is an integrated part of the device

driver library.

Table 426. CONTROL register bit assignments

Bits Name Function

[31:2] - Reserved

[1] Active stack

pointer

Defines the current stack:

0 = MSP is the current stack pointer

1 = PSP is the current stack pointer.

In Handler mode this bit reads as zero and ignores writes.

[0] - Reserved.