Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 461 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
For a Cortex-M0 microcontroller system, CMSIS defines:
• a common way to:
– access peripheral registers
– define exception vectors
• the names of:
– the registers of the core peripherals
– the core exception vectors
• a device-independent interface for RTOS kernels.
The CMSIS includes address definitions and data structures for the core peripherals in the
Cortex-M0 processor. It also includes optional interfaces for middleware components
comprising a TCP/IP stack and a Flash file system.
The CMSIS simplifies software development by enabling the reuse of template code, and
the combination of CMSIS-compliant software components from various middleware
vendors. Software vendors can expand the CMSIS to include their peripheral definitions
and access functions for those peripherals.
This document includes the register names defined by the CMSIS, and gives short
descriptions of the CMSIS functions that address the processor core and the core
peripherals.
Remark: This document uses the register short names defined by the CMSIS. In a few
cases these differ from the architectural short names that might be used in other
documents.
The following sections give more information about the CMSIS:
• Section 28.4.5.3 “Power management programming hints”
• Section 28.5.2 “Intrinsic functions”
• Section 28.6.2.1 “Accessing the Cortex-M0 NVIC registers using CMSIS”
• Section 28.6.2.8.1 “NVIC programming hints”.
28.4.2 Memory model
This section describes the processor memory map and the behavior of memory accesses.
The processor has a fixed memory map that provides up to 4GB of addressable memory.
The memory map is: