Datasheet

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User manual Rev. 12.3 — 10 June 2014 462 of 547
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UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
The processor reserves regions of the Private peripheral bus (PPB) address range for
core peripheral registers, see Section 28–28.3
.
28.4.2.1 Memory regions, types and attributes
The memory map is split into regions. Each region has a defined memory type, and some
regions have additional memory attributes. The memory type and attributes determine the
behavior of accesses to the region.
The memory types are:
Normal — The processor can re-order transactions for efficiency, or perform speculative
reads.
Device — The processor preserves transaction order relative to other transactions to
Device or Strongly-ordered memory.
See Figure 6 for the LPC111x/LPC11Cxx specific implementation of the memory map. SRAM and
code locations are different on the LPC111x/LPC11Cxx.
Fig 98. Generic ARM Cortex-M0 memory map
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