Datasheet
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User manual Rev. 12.3 — 10 June 2014 464 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
[1] See Section 28–28.4.2.1 for more information.
The Code, SRAM, and external RAM regions can hold programs.
28.4.2.4 Software ordering of memory accesses
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions. This is because:
• the processor can reorder some memory accesses to improve efficiency, providing
this does not affect the behavior of the instruction sequence
• memory or devices in the memory map might have different wait states
• some memory accesses are buffered or speculative.
Section 28–28.4.2.2
describes the cases where the memory system guarantees the order
of memory accesses. Otherwise, if the order of memory accesses is critical, software
must include memory barrier instructions to force that ordering. The processor provides
the following memory barrier instructions:
DMB — The Data Memory Barrier (DMB) instruction ensures that outstanding memory
transactions complete before subsequent memory transactions. See Section 28–28.5.7.3
.
DSB — The Data Synchronization Barrier (DSB) instruction ensures that outstanding
memory transactions complete before subsequent instructions execute. See
Section 28–28.5.7.4
.
ISB — The Instruction Synchronization Barrier (ISB) ensures that the effect of all
completed memory transactions is recognizable by subsequent instructions. See
Section 28–28.5.7.5
.
The following are examples of using memory barrier instructions:
Table 427. Memory access behavior
Address
range
Memory
region
Memory
type
[1]
XN
[1]
Description
0x00000000
-
0x1FFFFFFF
Code Normal - Executable region for program
code. You can also put data here.
0x20000000
-
0x3FFFFFFF
SRAM Normal - Executable region for data. You
can also put code here.
0x40000000
-
0x5FFFFFFF
Peripheral Device XN External device memory.
0x60000000
-
0x9FFFFFFF
External
RAM
Normal - Executable region for data.
0xA0000000
-
0xDFFFFFFF
External
device
Device XN External device memory.
0xE0000000
-
0xE00FFFFF
Private Peripheral
Bus
Strongly-ordered XN This region includes the NVIC,
System timer, and System Control
Block. Only word accesses can be
used in this region.
0xE0100000
-
0xFFFFFFFF
Device Device XN Vendor specific.