Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 47 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
3.8 Brown-out detection
The LPC111x/LPC11Cxx includes up to four levels for monitoring the voltage on the V
DD
pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt
signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable
Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the
signal by reading the NVIC status register (see Table 55
). Four threshold levels can be
selected to cause a forced reset of the chip (see Table 33
).
3.9 Power management
The LPC111x/LPC11Cxx support a variety of power control features. In Active mode,
when the chip is running, power and clocks to selected peripherals can be optimized for
power consumption. In addition, there are three special modes of processor power
reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode.
Remark: The Debug mode is not supported in Sleep, Deep-sleep, or Deep power-down
modes.
3.9.1 Active mode
In Active mode, the ARM Cortex-M0 core and memories are clocked by the system clock,
and peripherals are clocked by the system clock or a dedicated peripheral clock.
Fig 9. Start-up timing
valid threshold
= 1.8V
processor status
V
DD
IRC status
internal reset
GND
80 μs 101 μs
boot time
user code
boot code
execution
finishes;
user code starts
IRC
starts
supply ramp-up
time
55 μs