Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller HVQFN 32 (7x7) 32-Bit 50 MHz I/O number 28

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User manual Rev. 12.3 — 10 June 2014 474 of 547

NXP Semiconductors

UM10398

Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference

• angle brackets, <>, enclose alternative forms of the operand

• braces, {}, enclose optional operands and mnemonic parts

• the Operands column is not exhaustive.

For more information on the instructions and operands, see the instruction descriptions.

Table 430. Cortex-M0 instructions

Mnemonic Operands Brief description Flags Reference

ADCS {Rd,} Rn, Rm Add with Carry N,Z,C,V Section 28–28.5.5.1

ADD{S} {Rd,} Rn, <Rm|#imm> Add N,Z,C,V Section 28–28.5.5.1

ADR Rd, label PC-relative Address to Register - Section 28–28.5.4.1

ANDS {Rd,} Rn, Rm Bitwise AND N,Z Section 28–28.5.5.1

ASRS {Rd,} Rm, <Rs|#imm> Arithmetic Shift Right N,Z,C Section 28–28.5.5.3

B{cc} label Branch {conditionally} - Section 28–28.5.6.1

BICS {Rd,} Rn, Rm Bit Clear N,Z Section 28–28.5.5.2

BKPT #imm Breakpoint - Section 28–28.5.7.1

BL label Branch with Link - Section 28–28.5.6.1

BLX Rm Branch indirect with Link - Section 28–28.5.6.1

BX Rm Branch indirect - Section 28–28.5.6.1

CMN Rn, Rm Compare Negative N,Z,C,V Section 28–28.5.5.4

CMP Rn, <Rm|#imm> Compare N,Z,C,V Section 28–28.5.5.4

CPSID i Change Processor State, Disable

Interrupts

- Section 28–28.5.7.2

CPSIE i Change Processor State, Enable

Interrupts

- Section 28–28.5.7.2

DMB - Data Memory Barrier - Section 28–28.5.7.3

DSB - Data Synchronization Barrier - Section 28–28.5.7.4

EORS {Rd,} Rn, Rm Exclusive OR N,Z Section 28–28.5.5.2

ISB - Instruction Synchronization Barrier - Section 28–28.5.7.5

LDM Rn{!}, reglist Load Multiple registers, increment after - Section 28–28.5.4.5

LDR Rt, label Load Register from PC-relative address - Section 28–28.5.4

LDR Rt, [Rn, <Rm|#imm>] Load Register with word - Section 28–28.5.4

LDRB Rt, [Rn, <Rm|#imm>] Load Register with byte - Section 28–28.5.4

LDRH Rt, [Rn, <Rm|#imm>] Load Register with halfword - Section 28–28.5.4

LDRSB Rt, [Rn, <Rm|#imm>] Load Register with signed byte - Section 28–28.5.4

LDRSH Rt, [Rn, <Rm|#imm>] Load Register with signed halfword - Section 28–28.5.4

LSLS {Rd,} Rn, <Rs|#imm> Logical Shift Left N,Z,C Section 28–28.5.5.3

U {Rd,} Rn, <Rs|#imm> Logical Shift Right N,Z,C Section 28–28.5.5.3

MOV{S} Rd, Rm Move N,Z Section 28–28.5.5.5

MRS Rd, spec_reg Move to general register from special

- Section 28–28.5.7.6

MSR spec_reg, Rm Move to special register from general

N,Z,C,V Section 28–28.5.7.7

MULS Rd, Rn, Rm Multiply, 32-bit result N,Z Section 28–28.5.5.6

MVNS Rd, Rm Bitwise NOT N,Z Section 28–28.5.5.5