Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 475 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
28.5.2 Intrinsic functions
ISO/IEC C code cannot directly access some Cortex-M0 instructions. This section
describes intrinsic functions that can generate these instructions, provided by the CMSIS
and that might be provided by a C compiler. If a C compiler does not support an
appropriate intrinsic function, you might have to use inline assembler to access the
relevant instruction.
The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC
C code cannot directly access:
NOP - No Operation - Section 28–28.5.7.8
ORRS {Rd,} Rn, Rm Logical OR N,Z Section 28–28.5.5.2
POP reglist Pop registers from stack - Section 28–28.5.4.6
PUSH reglist Push registers onto stack - Section 28–28.5.4.6
REV Rd, Rm Byte-Reverse word - Section 28–28.5.5.7
REV16 Rd, Rm Byte-Reverse packed halfwords - Section 28–28.5.5.7
REVSH Rd, Rm Byte-Reverse signed halfword - Section 28–28.5.5.7
RORS {Rd,} Rn, Rs Rotate Right N,Z,C Section 28–28.5.5.3
RSBS {Rd,} Rn, #0 Reverse Subtract N,Z,C,V Section 28–28.5.5.1
SBCS {Rd,} Rn, Rm Subtract with Carry N,Z,C,V Section 28–28.5.5.1
SEV - Send Event - Section 28–28.5.7.9
STM Rn!, reglist Store Multiple registers, increment after - Section 28–28.5.4.5
STR Rt, [Rn, <Rm|#imm>] Store Register as word - Section 28–28.5.4
STRB Rt, [Rn, <Rm|#imm>] Store Register as byte - Section 28–28.5.4
STRH Rt, [Rn, <Rm|#imm>] Store Register as halfword - Section 28–28.5.4
SUB{S} {Rd,} Rn, <Rm|#imm> Subtract N,Z,C,V Section 28–28.5.5.1
SVC #imm Supervisor Call - Section 28–28.5.7.10
SXTB Rd, Rm Sign extend byte - Section 28–28.5.5.8
SXTH Rd, Rm Sign extend halfword - Section 28–28.5.5.8
TST Rn, Rm Logical AND based test N,Z Section 28–28.5.5.9
UXTB Rd, Rm Zero extend a byte - Section 28–28.5.5.8
UXTH Rd, Rm Zero extend a halfword - Section 28–28.5.5.8
WFE - Wait For Event - Section 28–28.5.7.11
WFI - Wait For Interrupt - Section 28–28.5.7.12
Table 430. Cortex-M0 instructions
Mnemonic Operands Brief description Flags Reference
Table 431. CMSIS intrinsic functions to generate some Cortex-M0 instructions
Instruction CMSIS intrinsic function
CPSIE i void __enable_irq(void)
CPSID i void __disable_irq(void)
ISB void __ISB(void)
DSB void __DSB(void)
DMB void __DMB(void)
NOP void __NOP(void)