Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 476 of 547
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UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
The CMSIS also provides a number of functions for accessing the special registers using
MRS and MSR instructions:
28.5.3 About the instruction descriptions
The following sections give more information about using the instructions:
Section 28.5.3.1 “Operands
Section 28.5.3.2 “Restrictions when using PC or SP
Section 28.5.3.3 “Shift Operations
Section 28.5.3.4 “Address alignment
Section 28.5.3.5 “PC-relative expressions
Section 28.5.3.6 “Conditional execution.
28.5.3.1 Operands
An instruction operand can be an ARM register, a constant, or another instruction-specific
parameter. Instructions act on the operands and often store the result in a destination
register. When there is a destination register in the instruction, it is usually specified before
the other operands.
28.5.3.2 Restrictions when using PC or SP
Many instructions are unable to use, or have restrictions on whether you can use, the
Program Counter (PC) or Stack Pointer (SP) for the operands or destination register.
See instruction descriptions for more information.
REV uint32_t __REV(uint32_t int value)
REV16 uint32_t __REV16(uint32_t int value)
REVSH uint32_t __REVSH(uint32_t int value)
SEV void __SEV(void)
WFE void __WFE(void)
WFI void __WFI(void)
Table 432. CMSIS intrinsic functions to access the special registers
Special register Access CMSIS function
PRIMASK Read uint32_t __get_PRIMASK (void)
Write void __set_PRIMASK (uint32_t value)
CONTROL Read uint32_t __get_CONTROL (void)
Write void __set_CONTROL (uint32_t value)
MSP Read uint32_t __get_MSP (void)
Write void __set_MSP (uint32_t TopOfMainStack)
PSP Read uint32_t __get_PSP (void)
Write void __set_PSP (uint32_t TopOfProcStack)
Table 431. CMSIS intrinsic functions to generate some Cortex-M0 instructions
Instruction CMSIS intrinsic function