Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 48 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
The chip is in Active mode after reset and the default power configuration is determined
by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers. The power
configuration can be changed during run time.
3.9.1.1 Power configuration in Active mode
Power consumption in Active mode is determined by the following configuration choices:
• The SYSAHBCLKCTRL register controls which memories and peripherals are
running (Table 21
).
• The power to various analog blocks (PLL, oscillators, the ADC, the BOD circuit, and
the flash block) can be controlled at any time individually through the PDRUNCFG
register (Table 44
).
• The clock source for the system clock can be selected from the IRC (default), the
system oscillator, or the watchdog oscillator (see Figure 8
and related registers).
• The system clock frequency can be selected by the SYSPLLCTRL (Table 10) and the
SYSAHBCLKDIV register (Table 20
).
• Selected peripherals (UART, SPI0/1, WDT) use individual peripheral clocks with their
own clock dividers. The peripheral clocks can be shut down through the
corresponding clock divider registers (Table 22
to Table 24).
3.9.2 Sleep mode
In Sleep mode, the system clock to the ARM Cortex-M0 core is stopped, and execution of
instructions is suspended until either a reset or an enabled interrupt occurs.
Peripheral functions, if selected to be clocked in the SYSAHBCLKCTRL register, continue
operation during Sleep mode and may generate interrupts to cause the processor to
resume execution. Sleep mode eliminates dynamic power used by the processor itself,
memory systems and their related controllers, and internal buses. The processor state
and registers, peripheral registers, and internal SRAM values are maintained, and the
logic levels of the pins remain static.
3.9.2.1 Power configuration in Sleep mode
Power consumption in Sleep mode is configured by the same settings as in Active mode:
• The clock remains running.
• The system clock frequency remains the same as in Active mode, but the processor is
not clocked.
• Analog and digital peripherals are selected as in Active mode.
3.9.2.2 Programming Sleep mode
The following steps must be performed to enter Sleep mode:
1. The DPDEN bit in the PCON register must be set to zero (Table 50
).
2. The SLEEPDEEP bit in the ARM Cortex-M0 SCR register must be set to zero, see
(Table 453
).
3. Use the ARM Cortex-M0 Wait-For-Interrupt (WFI) instruction.