Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 481 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
Table 433 also shows the relationship between condition code suffixes and the N, Z, C,
and V flags.
28.5.4 Memory access instructions
Table 434 shows the memory access instructions:
28.5.4.1 ADR
Generates a PC-relative address.
28.5.4.1.1 Syntax
ADR Rd, label
Table 433. Condition code suffixes
Suffix Flags Meaning
EQ Z = 1 Equal, last flag setting result was zero
NE Z = 0 Not equal, last flag setting result was non-zero
CS or HS C = 1 Higher or same, unsigned
CC or LO C = 0 Lower, unsigned
MI N = 1 Negative
PL N = 0 Positive or zero
VS V = 1 Overflow
VC V = 0 No overflow
HI C = 1 and Z = 0 Higher, unsigned
LS C = 0 or Z = 1 Lower or same, unsigned
GE N = V Greater than or equal, signed
LT N = V Less than, signed
GT Z = 0 and N = V Greater than, signed
LE Z = 1 and N = V Less than or equal, signed
AL Can have any value Always. This is the default when no suffix is specified.
Table 434. Access instructions
Mnemonic Brief description See
LDR{type} Load Register using register offset Section 28–28.5.4.
3
LDR Load Register from PC-relative address Section 28–28.5.4.
4
POP Pop registers from stack Section 28–28.5.4.
6
PUSH Push registers onto stack Section 28–28.5.4.
6
STM Store Multiple registers Section 28–28.5.4.
5
STR{type} Store Register using immediate offset Section 28–28.5.4.
2
STR{type} Store Register using register offset Section 28–28.5.4.
3