Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 482 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
where:
Rd is the destination register.
label is a PC-relative expression. See Section 28–28.5.3.5
.
28.5.4.1.2 Operation
ADR generates an address by adding an immediate value to the PC, and writes the result
to the destination register.
ADR facilitates the generation of position-independent code, because the address is
PC-relative.
If you use ADR to generate a target address for a BX or BLX instruction, you must ensure
that bit[0] of the address you generate is set to 1 for correct execution.
28.5.4.1.3 Restrictions
In this instruction Rd must specify R0-R7. The data-value addressed must be word
aligned and within 1020 bytes of the current PC.
28.5.4.1.4 Condition flags
This instruction does not change the flags.
28.5.4.1.5 Examples
ADR R1, TextMessage ; Write address value of a location labelled as
; TextMessage to R1
ADR R3, [PC,#996] ; Set R3 to value of PC + 996.
28.5.4.2 LDR and STR, immediate offset
Load and Store with immediate offset.
28.5.4.2.1 Syntax
LDR Rt, [<Rn | SP> {, #imm}]
LDR<B|H> Rt, [Rn {, #imm}]
STR Rt, [<Rn | SP>, {,#imm}]
STR<B|H> Rt, [Rn {,#imm}]
where:
Rt is the register to load or store.
Rn is the register on which the memory address is based.
imm is an offset from Rn. If imm is omitted, it is assumed to be zero.
28.5.4.2.2 Operation
LDR, LDRB and LDRH instructions load the register specified by Rt with either a word,
byte or halfword data value from memory. Sizes less than word are zero extended to
32-bits before being written to the register specified by Rt.