Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 484 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
28.5.4.3.2 Operation
LDR, LDRB, U, LDRSB and LDRSH load the register specified by Rt with either a word,
zero extended byte, zero extended halfword, sign extended byte or sign extended
halfword value from memory.
STR, STRB and STRH store the word, least-significant byte or lower halfword contained
in the single register specified by Rt into memory.
The memory address to load from or store to is the sum of the values in the registers
specified by Rn and Rm.
28.5.4.3.3 Restrictions
In these instructions:
• Rt, Rn, and Rm must only specify R0-R7.
• the computed memory address must be divisible by the number of bytes in the load or
store, see Section 28–28.5.3.4
.
28.5.4.3.4 Condition flags
These instructions do not change the flags.
28.5.4.3.5 Examples
STR R0, [R5, R1] ; Store value of R0 into an address equal to
; sum of R5 and R1
LDRSH R1, [R2, R3] ; Load a halfword from the memory address
; specified by (R2 + R3), sign extend to 32-bits
; and write to R1.
28.5.4.4 LDR, PC-relative
Load register (literal) from memory.
28.5.4.4.1 Syntax
LDR Rt, label
where:
Rt is the register to load.
label is a PC-relative expression. See Section 28–28.5.3.5
.
28.5.4.4.2 Operation
Loads the register specified by Rt from the word in memory specified by label.
28.5.4.4.3 Restrictions
In these instructions, label must be within 1020 bytes of the current PC and word aligned.
28.5.4.4.4 Condition flags
These instructions do not change the flags.