Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 487 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
• The exception is LR for a PUSH and PC for a POP.
28.5.4.6.4 Condition flags
These instructions do not change the flags.
28.5.4.6.5 Examples
PUSH {R0,R4-R7} ; Push R0,R4,R5,R6,R7 onto the stack
PUSH {R2,LR} ; Push R2 and the link-register onto the stack
POP {R0,R6,PC} ; Pop r0,r6 and PC from the stack, then branch to
; the new PC.
28.5.5 General data processing instructions
Table 435 shows the data processing instructions:
Table 435. Data processing instructions
Mnemonic Brief description See
ADCS Add with Carry Section 28–28.5.5.1
ADD{S} Add Section 28–28.5.5.1
ANDS Logical AND Section 28–28.5.5.2
ASRS Arithmetic Shift Right Section 28–28.5.5.3
BICS Bit Clear Section 28–28.5.5.2
CMN Compare Negative Section 28–28.5.5.4
CMP Compare Section 28–28.5.5.4
EORS Exclusive OR Section 28–28.5.5.2
LSLS Logical Shift Left Section 28–28.5.5.3
LSRS Logical Shift Right Section 28–28.5.5.3
MOV{S} Move Section 28–28.5.5.5
MULS Multiply Section 28–28.5.5.6
MVNS Move NOT Section 28–28.5.5.5
ORRS Logical OR Section 28–28.5.5.2
REV Reverse byte order in a word Section 28–28.5.5.7
REV16 Reverse byte order in each halfword Section 28–28.5.5.7
REVSH Reverse byte order in bottom halfword
and sign extend
Section 28–28.5.5.7
RORS Rotate Right Section 28–28.5.5.3
RSBS Reverse Subtract Section 28–28.5.5.1
SBCS Subtract with Carry Section 28–28.5.5.1
SUBS Subtract Section 28–28.5.5.1
SXTB Sign extend a byte Section 28–28.5.5.8
SXTH Sign extend a halfword Section 28–28.5.5.8
UXTB Zero extend a byte Section 28–28.5.5.8
UXTH Zero extend a halfword Section 28–28.5.5.8
TST Test Section 28–28.5.5.9