Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 49 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
3.9.2.3 Wake-up from Sleep mode
Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the
processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns
to its original power configuration defined by the contents of the PDRUNCFG and the
SYSAHBCLKDIV registers. If a reset occurs, the microcontroller enters the default
configuration in Active mode.
3.9.3 Deep-sleep mode
In Deep-sleep mode, the system clock to the processor is disabled as in Sleep mode. All
analog blocks are powered down, except for the BOD circuit and the watchdog oscillator,
which must be selected or deselected during Deep-sleep mode in the PDSLEEPCFG
register.
Deep-sleep mode eliminates all power used by the flash and analog peripherals and all
dynamic power used by the processor itself, memory systems and their related
controllers, and internal buses. The processor state and registers, peripheral registers,
and internal SRAM values are maintained, and the logic levels of the pins remain static.
3.9.3.1 Power configuration in Deep-sleep mode
Power consumption in Deep-sleep mode is determined by the Deep-sleep power
configuration setting in the PDSLEEPCFG (Table 42
) register:
• The only clock source available in Deep-sleep mode is the watchdog oscillator. The
watchdog oscillator can be left running in Deep-sleep mode if required for
timer-controlled wake-up (see Section 3.10.3
). All other clock sources (the IRC and
system oscillator) and the system PLL are shut down. The watchdog oscillator analog
output frequency must be set to the lowest value of its analog clock output (bits
FREQSEL in the WDTOSCCTRL = 0001, see Table 13
).
• The BOD circuit can be left running in Deep-sleep mode if required by the application.
• If the watchdog oscillator is running in Deep-sleep mode, only the watchdog timer or
one of the general-purpose timers should be enabled in SYSAHBCLKCTRL register
to minimize power consumption.
3.9.3.2 Programming Deep-sleep mode
The following steps must be performed to enter Deep-sleep mode:
1. The DPDEN bit in the PCON register must be set to zero (Table 50
).
2. Select the power configuration in Deep-sleep mode in the PDSLEEPCFG (Table 42
)
register.
a. If a timer-controlled wake-up is needed, ensure that the watchdog oscillator is
powered in the PDRUNCFG register and switch the clock source to WD oscillator
in the MAINCLKSEL register (Table 18
).
b. If no timer-controlled wake-up is needed and the watchdog oscillator is shut down,
ensure that the IRC is powered in the PDRUNCFG register and switch the clock
source to IRC in the MAINCLKSEL register (Table 18
). This ensures that the
system clock is shut down glitch-free.
3. Select the power configuration after wake-up in the PDAWAKECFG (Table 43
)
register.