Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 493 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
MVNS Rd, Rm
where:
S is an optional suffix. If S is specified, the condition code flags are updated on the
result of the operation, see Section 28–28.5.3.6
.
Rd is the destination register.
Rm is a register.
imm is any value in the range 0-255.
28.5.5.5.2 Operation
The MOV instruction copies the value of Rm into Rd.
The MOVS instruction performs the same operation as the MOV instruction, but also
updates the N and Z flags.
The MVNS instruction takes the value of Rm, performs a bitwise logical negate operation
on the value, and places the result into Rd.
28.5.5.5.3 Restrictions
In these instructions, Rd, and Rm must only specify R0-R7.
When Rd is the PC in a MOV instruction:
• Bit[0] of the result is discarded.
• A branch occurs to the address created by forcing bit[0] of the result to 0. The T-bit
remains unmodified.
Remark: Though it is possible to use MOV as a branch instruction, ARM strongly
recommends the use of a BX or BLX instruction to branch for software portability.
28.5.5.5.4 Condition flags
If S is specified, these instructions:
• update the N and Z flags according to the result
• do not affect the C or V flags.
28.5.5.5.5 Example
MOVS R0, #0x000B ; Write value of 0x000B to R0, flags get updated
MOVS R1, #0x0 ; Write value of zero to R1, flags are updated
MOV R10, R12 ; Write value in R12 to R10, flags are not updated
MOVS R3, #23 ; Write value of 23 to R3
MOV R8, SP ; Write value of stack pointer to R8
MVNS R2, R0 ; Write inverse of R0 to the R2 and update flags
28.5.5.6 MULS
Multiply using 32-bit operands, and producing a 32-bit result.
28.5.5.6.1 Syntax
MULS Rd, Rn, Rm