Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 495 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
REVSH — converts 16-bit signed big-endian data into 32-bit signed little-endian data or
16-bit signed little-endian data into 32-bit signed big-endian data.
28.5.5.7.3 Restrictions
In these instructions, Rd, and Rn must only specify R0-R7.
28.5.5.7.4 Condition flags
These instructions do not change the flags.
28.5.5.7.5 Examples
REV R3, R7 ; Reverse byte order of value in R7 and write it to R3
REV16 R0, R0 ; Reverse byte order of each 16-bit halfword in R0
REVSH R0, R5 ; Reverse signed halfword
28.5.5.8 SXT and UXT
Sign extend and Zero extend.
28.5.5.8.1 Syntax
SXTB Rd, Rm
SXTH Rd, Rm
UXTB Rd, Rm
UXTH Rd, Rm
where:
Rd is the destination register.
Rm is the register holding the value to be extended.
28.5.5.8.2 Operation
These instructions extract bits from the resulting value:
• SXTB extracts bits[7:0] and sign extends to 32 bits
• UXTB extracts bits[7:0] and zero extends to 32 bits
• SXTH extracts bits[15:0] and sign extends to 32 bits
• UXTH extracts bits[15:0] and zero extends to 32 bits.
28.5.5.8.3 Restrictions
In these instructions, Rd and Rm must only specify R0-R7.
28.5.5.8.4 Condition flags
These instructions do not affect the flags.