Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 496 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
28.5.5.8.5 Examples
SXTH R4, R6 ; Obtain the lower halfword of the
; value in R6 and then sign extend to
; 32 bits and write the result to R4.
UXTB R3, R1 ; Extract lowest byte of the value in R10 and zero
; extend it, and write the result to R3
28.5.5.9 TST
Test bits.
28.5.5.9.1 Syntax
TST Rn, Rm
where:
Rn is the register holding the first operand.
Rm the register to test against.
28.5.5.9.2 Operation
This instruction tests the value in a register against another register. It updates the
condition flags based on the result, but does not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value in
Rm. This is the same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with a register that has that bit
set to 1 and all other bits cleared to 0.
28.5.5.9.3 Restrictions
In these instructions, Rn and Rm must only specify R0-R7.
28.5.5.9.4 Condition flags
This instruction:
• updates the N and Z flags according to the result
• does not affect the C or V flags.
28.5.5.9.5 Examples
TST R0, R1 ; Perform bitwise AND of R0 value and R1 value,
; condition code flags are updated but result is discarded
28.5.6 Branch and control instructions
Table 437 shows the branch and control instructions:
Table 437. Branch and control instructions
Mnemonic Brief description See
B{cc} Branch {conditionally} Section 28–28.5.6.1