Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 498 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
• For BX and BLX, bit[0] of Rm must be 1 for correct execution. Bit[0] is used to update
the EPSR T-bit and is discarded from the target address.
Remark: Bcond is the only conditional instruction on the Cortex-M0 processor.
28.5.6.1.4 Condition flags
These instructions do not change the flags.
28.5.6.1.5 Examples
B loopA ; Branch to loopA
BL funC ; Branch with link (Call) to function funC, return address
; stored in LR
BX LR ; Return from function call
BLX R0 ; Branch with link and exchange (Call) to a address stored
; in R0
BEQ labelD ; Conditionally branch to labelD if last flag setting
; instruction set the Z flag, else do not branch.
28.5.7 Miscellaneous instructions
Table 439 shows the remaining Cortex-M0 instructions:
Table 439. Miscellaneous instructions
Mnemonic Brief description See
BKPT Breakpoint Section 28–28.5.7.
1
CPSID Change Processor State, Disable Interrupts Section 28–28.5.7.
2
CPSIE Change Processor State, Enable Interrupts Section 28–28.5.7.
2
DMB Data Memory Barrier Section 28–28.5.7.
3
DSB Data Synchronization Barrier Section 28–28.5.7.
4
ISB Instruction Synchronization Barrier Section 28–28.5.7.
5
MRS Move from special register to register Section 28–28.5.7.
6
MSR Move from register to special register Section 28–28.5.7.
7
NOP No Operation Section 28–28.5.7.
8
SEV Send Event Section 28–28.5.7.
9