Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 50 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
4. If an external pin is used for wake-up, enable and clear the wake-up pin in the start
logic registers (Table 37
to Table 40), and enable the start logic interrupt in the NVIC.
5. In the SYSAHBCLKCTRL register (Table 21
), disable all peripherals except
counter/timer or WDT if needed.
6. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register (Table 453
).
7. Use the ARM WFI instruction.
3.9.3.3 Wake-up from Deep-sleep mode
The microcontroller can wake up from Deep-sleep mode in the following ways:
• Signal on an external pin. For this purpose, pins PIO0_0 to PIO0_11 and PIO1_0 can
be enabled as inputs to the start logic. The start logic does not require any clocks and
generates the interrupt if enabled in the NVIC to wake up from Deep-sleep mode.
• Input signal to the start logic created by a match event on one of the general purpose
timer external match outputs. The pin holding the timer match function must be
enabled as start logic input in the NVIC, the corresponding timer must be enabled in
the SYSAHBCLKCTRL register, and the watchdog oscillator must be running in
Deep-sleep mode (for details see Section 3.10.3
).
• Reset from the BOD circuit. In this case, the BOD circuit must be enabled in the
PDSLEEPCFG register, and the BOD reset must be enabled in the BODCTRL
register (Table 33
).
• Reset from the watchdog timer. In this case, the watchdog oscillator must be running
in Deep-sleep mode (see PDSLEEPCFG register), and the WDT must be enabled in
the SYSAHBCLKCTRL register.
• A reset signal from the external RESET pin.
Remark: If the watchdog oscillator is running in Deep-sleep mode, its frequency
determines the wake-up time causing the wake-up time to be longer than waking up with
the IRC.
Remark: After wake-up, reprogram the clock source for the main clock.
3.9.4 Deep power-down mode
In Deep power-down mode, power and clocks are shut off to the entire chip with the
exception of the WAKEUP pin.
During Deep power-down mode, the contents of the SRAM and registers are not retained
except for a small amount of data which can be stored in the five 32-bit general purpose
registers of the PMU block.
All functional pins are tri-stated in Deep power-down mode except for the WAKEUP pin.
3.9.4.1 Power configuration in Deep power-down mode
Deep power-down mode has no configuration options. All clocks, the core, and all
peripherals are powered down. Only the WAKEUP pin is powered.
3.9.4.2 Programming Deep power-down mode
The following steps must be performed to enter Deep power-down mode: