Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 500 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
28.5.7.2.3 Restrictions
There are no restrictions.
28.5.7.2.4 Condition flags
This instruction does not change the condition flags.
28.5.7.2.5 Examples
CPSID i ; Disable all interrupts except NMI (set PRIMASK)
CPSIE i ; Enable interrupts (clear PRIMASK)
28.5.7.3 DMB
Data Memory Barrier.
28.5.7.3.1 Syntax
DMB
28.5.7.3.2 Operation
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that
appear in program order before the DMB instruction are observed before any explicit
memory accesses that appear in program order after the DMB instruction. DMB does not
affect the ordering of instructions that do not access memory.
28.5.7.3.3 Restrictions
There are no restrictions.
28.5.7.3.4 Condition flags
This instruction does not change the flags.
28.5.7.3.5 Examples
DMB ; Data Memory Barrier
28.5.7.4 DSB
Data Synchronization Barrier.
28.5.7.4.1 Syntax
DSB
28.5.7.4.2 Operation
DSB acts as a special data synchronization memory barrier. Instructions that come after
the DSB, in program order, do not execute until the DSB instruction completes. The DSB
instruction completes when all explicit memory accesses before it complete.
28.5.7.4.3 Restrictions
There are no restrictions.