Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 505 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
28.5.7.12.2 Operation
WFI
suspends execution until one of the following events occurs:
• an exception
• an interrupt becomes pending which would preempt if PRIMASK was clear
• a Debug Entry request, regardless of whether debug is enabled.
Remark: WFI is intended for power saving only. When writing software assume that WFI
might behave as a NOP operation.
28.5.7.12.3 Restrictions
There are no restrictions.
28.5.7.12.4 Condition flags
This instruction does not change the flags.
28.5.7.12.5 Examples
WFI ; Wait for interrupt
28.6 Peripherals
28.6.1 About the ARM Cortex-M0
The address map of the Private peripheral bus (PPB) is:
In register descriptions, the register type is described as follows:
RW — Read and write.
RO — Read-only.
WO — Write-only.
28.6.2 Nested Vectored Interrupt Controller
This section describes the Nested Vectored Interrupt Controller (NVIC) and the
registers it uses. The NVIC supports:
• 32 interrupts.
Table 440. Core peripheral register regions
Address Core peripheral Description
0xE000E008 - 0xE000E00F System Control Block Table 28–449
0xE000E010 - 0xE000E01F System timer Table 28–458
0xE000E100 - 0xE000E4EF Nested Vectored Interrupt Controller Table 28–441
0xE000ED00 - 0xE000ED3F System Control Block Table 28–449
0xE000EF00 - 0xE000EF03 Nested Vectored Interrupt Controller Table 28–441